This paper addresses the problem of transistor decomposition in channel length direction aiming at structured analog layout generation, manufacturability and low-power applications. We propose a channel decomposition method to generate structured layout for analog circuits with transistor array, and evaluate the error arising from the decomposition in both large and small signal analysis. The measurement results from a test chip suggests that the error can be ignored and the design with transistor array is applicable. Our test chip also demonstrates the effectiveness of design with transistor array with several typical analog circuits.
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