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ROOM TEMPERATURE DEPOSITED SiN: CHARACTERISATION AND APPLICATIONS IN MMICs

机译:室温沉积的SiN:表征及其在MMIC中的应用

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摘要

We present the mechanical and electrical characterisation of novel, high quality room temperature ammonia-free silicon nitride (SiN) films deposited using inductively coupled plasma enhanced chemical vapour deposition technique (ICP-CVD). Ultra thin 5 nm SiN Metal Insulator Metal (MIM) capacitors with 100% wafer yield were realised with a capacitance of 6.7 fF/μm~2 and a breakdown electric field of more than 3 x 10~6 Vcm~(-1). An increase in capacitance per unit area by more than thirteen fold with a reduction in RF loss was observed as the SiN film thickness was reduced from 120nm to 5nm. Comparison with high temperature conventional 300℃ PECVD SiN was also investigated; a comparable breakdown voltage, and leakage current was demonstrated. We also present the effect of the 5 nm SiN film deposited as an interface layer between the semiconductor and the metal of a Schottky contact for a sub 100nm gate length SiGe MODFETs. Finally, we report on an array-based design methodology for the realisation of Ⅲ-Ⅴ Monolithic Millimetre-wave Integrated Circuits (MMICs) enabled by the low temperature SiN deposition technique.
机译:我们介绍了使用电感耦合等离子体增强化学气相沉积技术(ICP-CVD)沉积的新型高质量室温无氨氮化硅(SiN)薄膜的机械和电气特性。以6.7 fF /μm〜2的电容和3 x 10〜6 Vcm〜(-1)的击穿电场实现了具有100%晶圆成品率的超薄5 nm SiN金属绝缘金属(MIM)电容器。随着SiN膜厚度从120nm减小到5nm,观察到每单位面积的电容增加了十三倍以上,同时RF损耗降低了。还研究了与高温常规300℃PECVD SiN的比较;具有可比的击穿电压和泄漏电流。我们还介绍了5nm SiN膜的沉积效果,该膜用作低于100nm栅极长度的SiGe MODFET的半导体和肖特基接触金属之间的界面层。最后,我们报告了一种基于阵列的设计方法,以实现通过低温SiN沉积技术实现的Ⅲ-Ⅴ单片毫米波集成电路(MMIC)。

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