A 12-bit fully differential 2MS/s successive approximation analog-to-digital converter with reduced power consumption

摘要

This paper presents a 12-bit fully differential successive approximation register analog-to-digital converter (ADC) operating at 2MS/s and designed for an optoelectronic range sensor as a system-on-chip device. The realized ADC uses several improvements to lower the power consumption to 10mW at 5V power supply and, at the same time, to increase the conversion rate up to the limits offered by the used 0.6µm process. The proposed interpolation network consists of partially segmented R-2R resistors ladder instead of the commonly used serial array to achieve lower power consumption as well as smaller active area. The fabricated chip occupies an active area of ∼1.1mm² excluding pads. Measurement data, resulting in an effective number of bits of 11.55 at 1MS/s and 11.2 at 2MS/s, conform to simulations. The maximum measured differential non-linearity and integral non-linearity accounts to +0.3/-0.6LSB and ±0.7LSB respectively.