Design of partially-asynchronous parallel processing elements for setting up Benes networks in O(log2N) time

摘要

Simple and fast processing elements for setting up Benes networks in parallel were demonstrated for the first time. All functions of the parallel processing elements were implemented with only hard-wired logic circuits, some of which operate asynchronously, for simplicity and speed. We developed the most critical elements for setting up a 16 × 16 Benes network. As a result, a preliminary design of the elements required only 67 slices (or about 1%) on an ordinary FPGA, and operated as fast as in only 20 clock cycles.