DFM based on layout restriction and process window verification for sub-60nm memory devices

摘要

The adoption of the model-based OPC and RET does not guarantee enough process margin any more in the low k1 lithography because potential patterning defects by layout-induced hot spots reduce common process window. The introduction of the litho-friendly layout has faced practical limitation by the designers' short knowledge of the lithography and its impact on the layout. In this paper, we develop a novel method based on restricted design rules (RDR) and process window verification (PWV) to get rid of the layout-related process hot spots during the physical layout design. Since RDR consists of simple design rules familiar to designers and PWV is implemented on layout editor environment, this proposed method is easy to apply in the current design flow. Since memory core layout is designed with typical and repeated patterns, the restriction of layout by design rule enforcement is effective to remove hot spots in the core area. We develop a systematic RDR extraction method by designing test patterns representing repeated memory core patterns by simple pattern matching technique. 1-dimensional (1D, simple line and space pattern) and 1.5-dimensional (1.5D, complicated line and space pattern) test patterns are analyzed to take into account the printability. The 2-dimension (2D) test patterns split by contact pad size are designed to consider the overlap margin between related layers. After removing the hot spots with RDR violations on unit cell by auto-fixer, PWV is applied to detect the random hot spots located on peripheral area. Analyzing CD difference between measurement and simulation according to variation of resist cutting plane and focus, the optical model having physical meaning is generated. The resist model, which uses focus exposure matrix (FEM) data within the process margin of memory cell, can represent the photo process variations accurately. Implementing the proposed method based on RDR and PWV, depth of focus (DOF) of sub-60nm memory device is improved by 50% compared with the result of original layout.