Some high performance digital integrated circuits use multi-phase clock distribution systems with level-sensitive latches as clocked storage elements. A set of N periodic non-overlapping binary clock signals propagate over each of the clock phase distribution networks and drive disjoint subsets of level-sensitive latches providing enhanced throughput and performance. This performance enhancement can result in increased area characteristics since the individual distribution networks are required for each clock phase. The method presented in this paper overcomes this problem by using a single global clock distribution network for a multi-valued (MV) clock signal in combination with level-sensitive latches designed to be transparent for a specific portion of the global MV clock signal. This approach is compatible with conventional binary logic since the only non-binary components required are the global clock generator and a modified literal selection gate that can be implemented as small analog circuits. A purely binary implementation approach is also described where the MV clock signal is replaced by a binary encoded signal and the phase-sensitive latches are implemented through the inclusion of a decoding function. This approach allows for implementation of the method using commercially available FPGA devices or a standard cell library containing only binary logic cells.
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