Methods for low insertion loss RF Switches with increased power handling capability in 65nm CMOS

摘要

This work reports on methods and dependencies for the design of low insertion loss single pole single throw (SPST) switches in 65nm CMOS with triple well transistors. Two different switch types are investigated and implemented. The series switch has less than 1dB insertion loss at 1.8GHz and a 1dB input compression point (P1dB) of 28.8dBm. The shunt switch has less than 0.4dB insertion loss at 1.8GHz and a P1dB of 29.1dBm. Isolation of the series and shunt switches at 1.8GHz is better than 21dB and 20dB, respectively. By applying a resistive body floating technique low insertion loss and increased power handling capability are achieved. At the shunt switch negative gate bias is adopted for improved P1dB. At the series switch a method is implemented to boost the DC voltage level at source/ drain nodes of transistors for improved power handling capability in off state without additional circuitry or any DC power consumption. The combination of these methods and an additional DC voltage in on state increases power handling capability in both states of the switch.