New Digit-Serial Systolic Arrays for Power-Sum and Division Operation in GF(2~m)

摘要

This paper implements a new digit-serial systolic array for the computation of a power-sum operation and a new digit-serial systolic divider using the proposed systolic power-sum array in GF(2~m) with the standard basis representation. Both of the architectures possess features of regularity, modularity, and unidirectional data flow. As a consequence, they have low AT complexity and are well suited to VLSI implementation with fault-tolerant design. Furthermore, the proposed power-sum array is also possible to select the digit-size of the regular square form.