Scaling Potential of 10nm Nanowire FET for Enhancing Gate Control

摘要

We utilize a three dimensional self-consistent Schr?dinger- Poisson solver based on the semi-empirical tight binding method to optimize 10 nm gate Silicon Nanowire Field Effect Transistors. Parameters sensitive to the device performance such as diameter of nanowire, gate oxide thickness and crystal axis are chosen to be varied to tune the device performance. Small signal analysis has been performed and critical parameters such as threshold voltage, subthreshold swing and ON/OFF current ratio are calculated from the simulation data. Our simulation results show that quantum nature of transport dominates in the interesting regime and can significantly enhances device performance. Thus sensitivity of device performance to the process variation at room temperature has been explored to meet the fabrication challenge of Nanowire based transistors.