An improved pass transistor synthesis method for low power, high speed CMOS circuits

摘要

A synthesis method for generating hybrid pass gate circuits is presented. These circuits combine features from both complementary CMOS arid pass gates architectures. The simulation results using a 0.7 μm technology show that circuits synthesized according to the proposed method may achieve significant improvements in terms of area: power and delay over traditional full swing pass transistor logic and complementary CMOS.