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Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage
Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage
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机译:使用具有降低的电荷泄漏的低功率/低阈值CMOS传输晶体管的存储单元
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摘要
A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.
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