In this paper, we present a standard cell design methodology for Spin Wave Device (SWD) circuits. We perform Place and Route (P&R) experiments against a 10nm FinFET CMOS technology and compare the area, the routing and metal distribution of several arithmetic benchmarks. We show that SWD circuits although they require more metal layers than CMOS designs and although they contain double the number of nets, their pin density and net length distribution makes them easier (2× shorter nets) and cheaper (13% less wiring required) to route than CMOS, without impact the area of the designs.
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