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Mitigation of NBTI Induced Performance Degradation in On-Chip Digital LDOs

机译:减轻芯片数码LDO中的NBTI诱导性能下降

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On-chip digital low-dropout voltage regulators (LDOs) have recently gained impetus and drawn significant attention for integration within both mobile devices and micro-processors. Although the benefits of easy integration and fast response speed surpass analog LDOs and other voltage regulator types, NBTI induced performance degradation is typically overlooked. The conventional bi-directional shift register based controller can even exacerbate the degradation, which has been demonstrated theoretically and through practical applications. In this paper, a novel uni-directional shift register is proposed to evenly distribute the electrical stress and mitigate the NBTI effects under arbitrary load conditions with nearly no extra power and area overhead. The benefits of the proposed design as well as reliability aware design considerations are explored and highlighted through simulation of an IBM POWER8 like processor under several benchmark applications. It is demonstrated that the proposed NBTI-aware design can achieve up to 43.2% performance improvement as compared to a conventional one.
机译:片上数字低压丢失电压调节器(LDO)最近获得了动力,并在移动设备和微处理器中汲取了集成的重大关注。虽然易于集成和快速响应速度超越模拟LDO和其他电压调节器类型的好处,但通常忽略了NBTI诱导的性能下降。传统的双向移位寄存器的控制器甚至可以加剧理论上和通过实际应用已经证明的降解。在本文中,提出了一种新颖的单向移位寄存器,以均匀地分布电力应力并在任意负载条件下减轻NBTI效应,几乎没有额外的功率和面积开销。通过在几个基准应用程序下,通过仿真,探讨了所提出的设计以及可靠性意识设计考虑的优势,并突出显示了IBM Power8,如处理器。结果表明,与传统的,所提出的NBTI感知设计可以达到高达43.2%的性能改进。

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