An on-chip sensor to measure and compensate static NBTI-induced degradation in analog circuits

摘要

Negative Bias Temperature Instability (NBTI) degrades the life-time of both the analog and digital circuits significantly and has become a major concern in nanoscale regime. In analog circuits, the DC biasing voltage is always present irrespective of the input signal. Therefore, coupled with high operating temperature (due to dynamic switching and high packaging density of SoC) and constant DC bias, there would be continuous NBTI stress in analog circuits with minor or almost no recovery. Moreover, mismatch and input referred offset voltage caused by NBTI in differential pairs, current sources and cascode stages can cause instantaneous, intermittent or catastrophic failure after certain time period. The problem of NBTI is usually addressed by leaving large design margins and/or employing adaptive body bias and dynamic voltage scaling calibration techniques using on-chip sensors or monitors. We propose an ultra low power and low area on-chip NBTI sensor which can be used to accurately sense the NBTI degradation in analog circuits. We have shown that the temporal degradation of PMOS transistor in analog circuits has high correlation to the output variation in proposed NBTI sensor. We also propose a simple circuit for generating accurate body bias to compensate temporal NBTI. We have demonstrated how using the proposed sensor and the adaptive body bias mechanism can be used to compensate NBTI degradation in various analog circuits. Measurement results are also provided for the proposed sensor fabricated in commercially available 65 nm process.