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Modeling of Charge Loss Mechanisms during the Short Term Retention Operation in 3-D NAND Flash Memories

机译:3-D NAND闪存中短期保留操作期间电荷损耗机制建模

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Right after program, stored electrons in the shallow nitride trap level can be released less than a few seconds. By setting the delay between program and reading phase to as small as 10μs, we found that several mechanisms are mixed when stored electrons are emitted during short term retention of 3-D NAND Flash. For the first time, we have confirmed that the charge loss mechanisms consist of three mechanisms and have separated each mechanism. In particular, the vertical redistribution of electrons in the charge trap layer, observed only during short term, was analyzed for the first time. Short term retention data measured at various temperatures (25-115°C) and at several program verify levels (PV3, PV5, PV7) in solid (S/P) and checker-board patterns (C/P) were analyzed using our model. Finally, the activation energy (Ea) of each mechanism was extracted by the Arrhenius law and the magnitudes of Ea were compared.
机译:在程序之后,浅氮化物阱水平中的存储电子可以释放小于几秒钟。通过将程序与读取阶段之间的延迟设定为小于10μs,发现当在短期保留3-D NAND闪光期间被存储的电子发射时混合了多种机制。我们首次证实了电荷损失机制由三种机制组成,并分开了每种机制。特别地,仅在短期内观察到电荷陷阱层中的电子的垂直再分布,首次分析。使用我们的模型分析了在各种温度(25-115°C)和若干程序验证水平(PV3,PV5,PV7)下测量的短期保留数据(PV3,PV5,PV7),并使用我们的模型分析。最后,激活能量(e a )每个机制由Arrhenius Lave和E的大小提取 a 比较了。

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