NAND CHARGE CYCLING BY EQUALIZING AND REGULATING THE SOURCE WELL AND BIT LINES DURING WRITE OPERATIONS FOR NAND FLASH MEMORY

摘要

In non-volatile memory devices, writing is typically configured with a set of alternating pulse and verify operations. At the end of the pulse, the device should be appropriately biased for correct verification, after which the device is again biased for the next pulse. The intervals between the pulse phase and the verify phase are considered. After the pulse, but before the verify conditions are established, during the interval, the source, bit lines and, optionally, the well may be equalized and regulated to the desired DC level. After the verify phase, but before biasing the memory for the next pulse, the source and bit lines may be equalized to the DC level. In some cases the non-volatile memory is programmed with a set of alternating pulses, but for at least some pulses it is programmed without any intervening verify operations. After one pulse, however, the source and bit line levels may be left floating before the intervening verification biases the memory for the next pulse.