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Modeling of Charge Loss Mechanisms during the Short Term Retention Operation in 3-D NAND Flash Memories

机译:3-D NAND闪存中短期保留操作期间的电荷损失机制建模

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Right after program, stored electrons in the shallow nitride trap level can be released less than a few seconds. By setting the delay between program and reading phase to as small as 10μs, we found that several mechanisms are mixed when stored electrons are emitted during short term retention of 3-D NAND Flash. For the first time, we have confirmed that the charge loss mechanisms consist of three mechanisms and have separated each mechanism. In particular, the vertical redistribution of electrons in the charge trap layer, observed only during short term, was analyzed for the first time. Short term retention data measured at various temperatures (25-115°C) and at several program verify levels (PV3, PV5, PV7) in solid (S/P) and checker-board patterns (C/P) were analyzed using our model. Finally, the activation energy (Ea) of each mechanism was extracted by the Arrhenius law and the magnitudes of Ea were compared.
机译:编程后,可以在不到几秒钟的时间内释放出浅氮化物陷阱能级中存储的电子。通过将编程和读取阶段之间的延迟设置为10μs,我们发现在3-D NAND闪存的短期保留期间,当存储的电子被发射时,多种机制混合在一起。我们首次确认电荷损失机制由三个机制组成,并且已将每个机制分开。特别是,首次分析了仅在短期内观察到的电荷陷阱层中电子的垂直重新分布。使用我们的模型分析了在不同温度(25-115°C)和几个程序验证水平(PV3,PV5,PV7)下以固体(S / P)和棋盘图案(C / P)测得的短期保留数据。最后,活化能(E a )的每个机制均通过阿伦尼乌斯定律和E的幅度提取 a 进行比较。

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