A model of 4-bit multiplier having low power and high speed using Algorithm named Dadda is proposed here and the basic building block used is optimized Full adder having low power dissipation and minimum propagation delay. Full and half adder blocks have been designed using pass-transistor logic and CMOS process technology to reduce the power dissipation and propagation delay. The model has been designed using Tanner EDA in 90nm technology. The proposed multiplier starts its operation at the supply of 1V.
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