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Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders
Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders
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机译:使用4位乘4位乘法器和级联加法器的快速n位乘n位乘法器
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摘要
A method and apparatus for n-bit by n-bit multiplication is disclosed using paralleled 4-bit by 4-bit multipliers and cascaded adder structures. The cascaded adder structures may be used to produce non-pipelined, integer, n-bit by n-bit multipliers with higher throughput than systolic array multipliers of similar geometries.
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