FAST N-BIT BY N-BIT MULTIPLIERS USING 4-BIT BY 4-BIT MULTIPLIERS AND CASCADED ADDERS

摘要

A method and apparatus for n-bit by n-bit multiplication are disclosed using paralleled 4-bit by 4-bit multipliers and cascaded adder structures. The cascaded adder structures may be used to produce non-pipelined, integer, n-bit by n-bit multipliers with higher throughput than systolic array multipliers of similar geometries.