Hierarchical Floorplanning Based on Analog Structure Tree

摘要

In a hierarchical optimization framework for analog designs, we introduce an analog structure tree to floorplanning which consists of device-, circuit-, structure-, and function-level groups. The structure tree is constructed such that each node corresponds to a proximity or a symmetry constraint is consistent with the layout. Furthermore, we modularize nodes at a specified level of the analog structure tree and deal with them as soft modules in floorplanning. In experiments, we demonstrate our system generates a reasonable layout of typical analog circuits at a surprising speed compared with manual design.