Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process

摘要

A clock generator is an important part of most systems as it is used for synchronization and data processing. For low-power operations, an all-digital phase-locked loop (ADPLL) is a suitable implementation of a clock generator for wireless sensing applications. Design decisions in different levels of abstraction were done to further reduce the power of an implemented ADPLL. It was shown that its power consumption can be minimized by at most 70%. Moreover, the output frequency of the ADPLL ranges from 0.286 - 18MHz with a power consumption of 4.606μW at 18MHz.