Various applications ranging from digital signal processing to cryptography require the usage of efficient multipliers. Many algorithms have been proposed in order to improve the speed while making use of lesser resources. There are 16 sutras or algorithms described in the Vedic literature for multiplication. This work makes use of Urdhva Tiryakbhyam Sutra, one among the 16 sutras and the same has been modified so as to make it more efficient. The modified vedic multiplier needs four n/2- bit vedic multipliers and three adders. Power, timing and device utilization analysis of large key lengths 174- bits, 194- bits, 233- bits using Vedic, Karatsuba and Booth algorithms are compared. All the three algorithms have been synthesized and implemented using Xilinx FPGA Virtex-6 xc6vlx760.
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