CONCURRENT ARCHITECTURE OF VEDIC MULTIPLIER-AN ACCELERATOR SCHEME FOR HIGH SPEED COMPUTING

摘要

Present invention provides Concurrent Architecture of Vedic Multiplier-An Accelerator Scheme for High Speed Computing. The methodblogy of applying Vedic fundamentals greatly optimizes the constraints like Power, Time, Area and Hardware Resource Utilization. And can be; proven for development of Efficient and Secured Templates. Vedic mathematics deeply removes the intermediate steps and gives direct output, for complex procedures like multiplication. The said procedure has wide applications in Encryption, Decryption, Image Processing, Signal Processing, Secured · Wireless Sensor j Network, Cloud Computing, Error Correction and Detection Modules and etc. all these applications has one common block of multiplier, which is complex procedure at hardware level. Hence, a need of high speed Multiplication can be fulfilled by implemented Novel Vedic Multiplier using blocks of concurrently executable hardware architecture like FPGA. Following invention is described in detail, with the -help of Figure 1 of sheet 1 showing the block diagram of the architecture of Vedic Multiplier.