Compressor Based Area-Efficient Low-Power 8x8 Vedic Multiplier

摘要

Multipliers are the integral components in the design of many high performance FIR filters, image and digital signal processors. Multipliers being the most area and power co nsuming elements of a design, area-efficient low-po wer multiplier architectures are in demand. In this paper, multiplier based on ancient Ved ic mathematics technique has been proposed which emplo ys 4:3, 5:3, 6:3 and 7:3 compressors for addition of partial products. Combining the Vedic Sutra- Urdhwa Tiryakbhyam and efficient compressors, a robust area and power efficient multiplier architecture has been achieved. The designs were synthesized and analysed in Cadence RTL compiler in 180 nm technology. When compared with previous compressor based multiplier, the proposed design achieves 30.5% and 25.8% reduction in power and area respectively