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Characteristics of a Schottky barrier diode and the SiC wafers sliced by wire electrical discharge machining

机译:肖特基势垒二极管的特点和线电气放电加工切片的SiC晶片

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The multi-wire electrical discharge slicing (multi-wire EDS), which is a brand-new method for fabricating wafers, is expected to considerably reduce the production cost of SiC wafers by decreasing in the width of kerf and kerf loss. We evaluated, for the first time, the influences of a wire electrical discharge machining (WEDM) on the SiC wafers based on experiments using WEDM equipped with a power supply of EDS. Although the analyses by transmission electron microscopy (TEM) and energy dispersive X-ray (EDX) revealed that the WEDM influenced layer consisted of a contamination layer including several kinds of metals and a layer having crystal defects was certainly formed near the wafer surfaces, the width of the influenced layers was only 3μm, and the layer could be easily removed by the grinding process. Furthermore, characteristics of Schottky barrier diodes (SBDs) fabricated with removing the influenced layer formed by WEDM are comparable to those fabricated with using conventional wafers. 1. Introduction SiC is an attractive material for power devices, because of its excellent electrical properties. While the demand of SiC for power devices is increasing, reduction of wafer production cost is required due to a valuable SiC ingot. Hence, it is effective to increase, numbers of wafers which are obtained from one ingot. The increase in wafers can be expected by reduction of kerf loss during slicing, whereas it is very difficult to slice a SiC ingot into wafers with a narrow kerf due to its hardness. It is difficult for conventional multi-wire saw to use thin line wires which is effective to reduce kerf loss. In the case of slicing of SiC ingot by wire-saw with thin line wire, the slicing speed must be slow to prevent wire breakage. In order to resolve this problem, we have proposed the multi-wire EDS for wafer manufacturing method as shown in the Fig. 1 [1]. In the multi-wire EDS, a large reactive force does not act on the wire throughout the process because of noncontact removal machining with the heat of electrical discharge. Essentially, thin line wires can be used on the multi-wire EDS, since the wire is not influenced by hardness of a SiC ingot. In particular, the multi-wire EDS is expected as the effective method for slicing the large-diameter wafers from the large SiC ingot. On the other hand, the multi-wire EDS might spoil the attractive characteristic of SiC wafers due to contaminations of several kinds of metals which are mixed in a processing atmosphere or due to considerably local high temperature more than sublimation temperature. In this paper, we report the characteristics of a SBD fabricated with SiC wafers sliced by WEDM based on the investigation about properties of the influenced layer.
机译:这是一种用于制造晶片的全新方法的多线电放电切片(多线EDS),预计通过减少Kerf和Kerf损失的宽度来显着降低SiC晶片的生产成本。我们首次评估了基于使用具有EDS电源的WEDM的实验基于SIC晶片对SiC晶片的电线电放电加工(WEDM)的影响。尽管通过透射电子显微镜(TEM)和能量分散X射线(EDX)的分析显示,WEDM影响层由包括几种金属的污染层组成,并且肯定在晶片表面附近形成具有晶体缺陷的层。受影响的层的宽度仅为3μm,并且可以通过研磨过程容易地除去层。此外,用去除由WEDM形成的影响层制造的肖特基势垒二极管(SBD)的特性与使用常规晶片制造的那些相当。 1.引言SiC是一种有吸引力的电力器件材料,因为其电气性能优异。虽然SiC用于电力设备的需求正在增加,但由于有价值的SiC铸锭,需要减少晶片生产成本。因此,增加从一个铸锭获得的晶片数量有效。通过在切片期间减少kerf损耗,可以预期晶片的增加,而由于其硬度,将SiC锭切成晶片中的晶锭。传统的多线锯难以使用细线线,这有效地减少截止损耗。在通过带有细线线的线锯切割SiC锭的情况下,切片速度必须缓慢以防止断线。为了解决这个问题,我们提出了如图1 [1]所示的晶片制造方法的多线EDS。在多线EDS中,由于具有电气的热量的不接触的去除加工,在整个过程中,大的反作用力不会作用在整个过程中。基本上,薄线线可以在多线ED上使用,因为线不会受到SiC锭的硬度的影响。特别地,多线EDS预期是从大型SiC锭切割大直径晶片的有效方法。另一方面,由于几种金属的污染,多线EDS可能会破坏SiC晶片的有吸引力的特征,这在加工气氛中混合或由于大于升华温度的显着局部高温。在本文中,我们报道了由WEDM切成的SiC晶片制造的SIC晶片的特性,基于受影响层的性质的研究。

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