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Impact of interface traps on current-voltage characteristics of 4H-SiC Schottky-barrier diodes

机译:接口陷阱对4H-SIC肖特基屏障二极管电流电压特性的影响

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This paper presents a physical model based on interface traps to explain both the larger barrier heights of practical Schottky diodes in comparison to the theoretically expected values and the appearance of a knee in the log I-V characteristics. According to this model, acceptor-type interface traps near the valance band increase the Schottky barrier height, which shifts the log I-V characteristic to higher forward-bias voltages. In addition to the acceptor traps, donor-type interface traps can appear near the conduction band, and when they do, they cause the knee in the log I-V characteristics as their energy level falls below the Fermi level and the charge associated with these traps changes from positive to neutral.
机译:本文介绍了基于界面陷阱的物理模型,以解释实际肖特基二极管的较大屏障高度与理论上预期的值和日志I-V特性中的膝关节的外观相比。根据该模型,遵循帷幔频带附近的受体型接口陷阱增加了肖特基势垒高度,使日志I-V特性转换到更高的前向偏置电压。除了受接受陷阱之外,捐赠型界面陷阱可以出现在导通带附近,并且当它们确实时,它们会导致LOG IV特性的膝盖,因为它们的能级低于费米水平,并且与这些陷阱相关的电荷变化从阳性到中性。

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