MEPTEC Roadmaps 2013 Session 1 Notes

摘要

Product requirements drive both wafer process nodes and package technology forward. Processor, ASIC, and FPGA advances have driven the industry to nano-scale geometries and 300 mm wafer size for silicon, and to flip chip interconnect and 2.5 / 3D technologies for packaging. Requirements in device functionality, power, speed, and mobility continue to drive the packaging roadmap. We shall assemble a panel of product packaging experts, including representatives from different semiconductor device and system markets, to discuss their packaging roadmaps and the challenges therein.