Inspection and Metrology for 2.5/3D Interconnect Victor Vartanian 3D Interconnect Enablement Center SEMATECH - (PPT)

摘要

FEOL processing (new metrology challenges); High A/R TSVs; TSV liners; Cu metallization; MEOL processing (new metrology challenges); Wafer stacking; Edge trim; Bond void; Wafer thinning; TSV reveal; Bump metallization; BEOL stacking and assembly (conventional metrology, but challenges due to scaling and tighter tolerances); Packaging-defective bond joints and underfill defects; Smaller features and higher tolerance requirements than MEMS or PCB applications; Aggressive die thicknesses, currently, 50-100 μm thick die and interposers; Microbumps as small as 20 μm diameter/40 μm pitch; Multi-tier packages and small gap distances.