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Design of single neuron on FPGA

机译:FPGA上单根神经元的设计

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This paper presents a digital design of neuron architecture on field-programmable gate array (FPGA). The objective of this project is to translate data from electrochemical sensor signals and process the data with neuron structure on digital hardware. The hardware realization of neural network requires investigation of many design issues relating to signal interfacing and design of a single neuron. Analysis focuses on effect of digital design decisions such as module architecture towards data accuracy and delay. The work touches on analogue to digital interfacing, data structure and digital module design that includes adder, multiplier and multiplier accumulator (MAC). A major component of the algorithm is the design of the activation function. The chosen activation function is the hyperbolic tangent which is approximated by Taylor Series expansion. The neuron is evaluated on an Altera DE2–70 FPGA. The performances are evaluated in terms of functionality, usage of resources and timing analysis. For the data structure, it was demonstrated that increasing the fractional bits will increases the precision. The neuron functionality was demonstrated on digital platform. It was found that less delay were produce by using Carry Look Ahead design compared to Ripple Carry Adder by 25% in the MAC performance.
机译:本文介绍了现场可编程门阵列(FPGA)上的神经元架构的数字设计。该项目的目的是将数据从电化学传感器信号转换,并在数字硬件上处理具有神经元结构的数据。神经网络的硬件实现需要调查与信号接口有关的许多设计问题,单个神经元的设计。分析侧重于模块架构等数字设计决策的效果,以实现数据准确性和延迟。该工作涉及模拟以数字接口,数据结构和数字模块设计,包括加法器,乘法器和乘法器累加器(MAC)。算法的主要组成部分是激活功能的设计。所选择的激活函数是泰勒系列扩展近似的双曲线切线。在Altera DE2-70 FPGA上评估神经元。在功能性,资源使用和定时分析方面评估性能。对于数据结构,证明了增加分数位将增加精度。在数字平台上证明了神经元功能。结果发现,通过使用携带的延迟较少,与纹波相比,在MAC性能下,涟漪将加法器携带加速度较少。

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