Reduction of Test Data Volume Using DTESFF-Based Partial Enhanced Scan Method

摘要

Scan architecture is widely used method for testing of transition delay faults (TDF). Launch-on-capture (LOC) and Launch-on-shift (LOS) are methods in scan-based test. In scan-based test all the possible combinations of two pattern delay tests cannot be applied to the circuit under test due to the structural constraints of scan which results in poor test coverage. This problem is alleviated in enhanced scan method as it supports random test vectors for delay test vector pairs at the cost of significant area overhead. The area overhead for enhanced scan chain method can be reduced by replacing the redundant flip-flop with the hold latch in enhanced scan flip-flop. Hold latch based enhanced scan design needs a fast hold signal similar to scan-enable signal in LOS testing. Delay Testable Enhanced Scan Flip-Flop (DTESFF) implements the enhanced scan cell with the slow hold signal. In this work, DTESFF-based partial enhanced scan method is proposed for the reduction of test data volume. Simulation results on ISCAS '89 benchmark circuit displays reduction of test data volume.