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Study of selective 'chemical downstream plasma etching' of silicon nitride and silicon oxide for advanced patterning applications

机译:氮化硅和氧化硅的选择性“化学下游等离子体蚀刻”,用于先进的图案化应用

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The evolution of integrated components in the semiconductors industry is nowadays looking for ultra-high selective etching processes in order to etch high aspect ratio structures in complicated stacks of ultrathin layers. For ultra-high selective processes, typical plasma etching show limitations, while wet etching processes reach limitations due to capillary forces. For these reasons there is a great regain of interest today in chemical downstream etching systems(CDE), which combine the advantages of plasma and wet treatments. The absence of photons and ions allow to minimize damages and to achieve very high selectivity (in isotropic etching). In this work we investigated the parameters enabling to etch selectively the Si_3N_4 to the SiO_2 by CDE. We shown that the correlation between the gas mixture and the wafer temperature is the key to obtain the desired selectivity. In order to optimize the processing window, the mixture composition (NF_3/N_2/O_2/He) and the temperatures were screened by seveverals DOE (Designs Of Experiments). Conditions are found in which the etching selectivity between the two silicon alloys is higher than 100, which allowed us to clean out sacrificial Si_3N_4 layers in very high aspect ratio (about 100) silicon trenches of nanometric size (60nm) without damaging the 10nm thin SiO_2 caping layer (between the Si and the Si3N4). This demonstrates that downstream plasma etching can perform better than wet treatments in this case.
机译:如今,半导体工业中的集成部件的演化现在正在寻找超高选择性蚀刻工艺,以蚀刻在超薄层的复杂叠层中的高纵横比结构。对于超高选择性过程,典型的等离子体蚀刻显示限制,而湿法蚀刻过程由于毛细管力而达到限制。由于这些原因,今天在化学下游蚀刻系统(CDE)中有一个令人兴奋的令人兴奋,这与血浆和湿法处理的优点相结合。没有光子和离子允许最小化损伤并实现非常高的选择性(在各向同性蚀刻中)。在这项工作中,我们调查了通过CDE选择性地将Si_3N_4蚀刻到Si_3N_4的参数。我们表明,气体混合物与晶片温度之间的相关性是获得所需选择性的关键。为了优化处理窗口,通过SeveMerals DOE(实验设计)筛选混合物组合物(NF_3 / N_2 / O_2 / HE)和温度。发现条件,其中两个硅合金之间的蚀刻选择性高于100,这使我们允许我们在非常高的纵横比(约100)纳米尺寸(60nm)的硅沟槽中清洁牺牲Si_3N_4层,而不会损坏10nm薄的SiO_2胶束层(在Si和Si3N4之间)。这表明下游等离子体蚀刻可以在这种情况下比湿法处理更好。

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