A CMOS APS Arrays with TDI in Analog Voltage Domain

摘要

CMOS APS sensors suffer from the SNR reduction caused by the decrease in integration time, especially under the case of low light condition and high relative velocity between objects and sensors. In this paper, a new APS circuits architecture by which TDI function is implemented in the analog voltage domain is proposed to overcome this problem. Time delay integration operation is a straightforward method comes from good old CCD sensors in which signals are added in charge packages with low noise. In this design TDI is mainly achieved by the switch capacitor accumulators and corresponding timing sequences implemented by digital logic on chip. The main noise source especially come from analog sample hold capacitors and OPA are analyzed. The offsets and FPNs are reduced by auto-zero operation and double difference sampling. A 16×128 3T TDI pixel arrays has been taped out by CSMC 0.5 um technology. And finally from the simulation results, a 10dB/dec SNR increase in terms of TDI level has been achieved under low light condition.