首页> 外国专利> DIGITAL DOMAIN ACCUMULATIVE CMOS-TDI IMAGE SENSOR WITH LOW POWER CONSUMPTION

DIGITAL DOMAIN ACCUMULATIVE CMOS-TDI IMAGE SENSOR WITH LOW POWER CONSUMPTION

机译:具有低功耗的数字域累积CMOS-TDI图像传感器

摘要

The present invention relates to the field of design of analog digital hybrid integrated circuit. The object of the invention is to reduce ADC conversion rate thus further reducing power consumption of the sensor while not reducing line frequency of the CMOS-TDI. To this end, a digital domain accumulative CMOS-TDI image sensor with low power consumption is provided. It includes a pixel array of n+k lines multiplied m columns, a column parallel signal pre-processing circuit, a column parallel successive approximation (SAR) ADC, a column parallel digital domain accumulator, a column parallel divider, a timing control circuit and an output shift register, wherein n+k+1 coarse quantification memory units are provided to the column parallel digital domain accumulator for storage of coarse quantification results; and memory units for storage of n times of fine quantification results are also provided, thus realizing n stages of TDI signal accumulation after accumulation of n times of fine quantification results. The invention is generally used in hybrid integrated circuit design.
机译:本发明涉及模拟数字混合集成电路的设计领域。本发明的目的是降低ADC转换速率,从而进一步降低传感器的功耗,同时又不降低CMOS-TDI的线路频率。为此,提供了具有低功耗的数字域累积CMOS-TDI图像传感器。它包括n + k行乘以m列的像素阵列,列并行信号预处理电路,列并行逐次逼近(SAR)ADC,列并行数字域累加器,列并行除法器,时序控制电路和输出移位寄存器,其中n + k + 1个粗量化存储单元被提供给列并行数字域累加器,用于存储粗量化结果;还提供了用于存储n次精细量化结果的存储单元,从而在n次精细量化结果累加后实现了n个阶段的TDI信号累加。本发明通常用于混合集成电路设计中。

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