Design of a 20Gb/s 4-tap adaptive decision feedback equalizer in 40nm CMOS

摘要

In this paper, a 20Gb/s 4-tap adaptive decision feedback equalizer (DFE) is proposed for high speed backplane communication, which includes a high-speed Finite impulse response filter (FIR), two amplifiers and an adaptation unit based on Sign-Sign Least-Mean-Square Error (SSLMS) algorithm. The FIR consists of samplers, an adder and Delay units. In order to realize a high speed, half-rate structure and current mode logic (CML)[6] are employed. Simulation result show that 20Gb/s data rate with horizontal eye opening of outputs is larger than 0.8UI.