Clock signal regeneration method for receiver circuit uses Baud rate sampling with forward feedback equalizer and adaptive decision feedback equalizer

摘要

The clock signal recovery method uses Baud rate sampling of an input signal (u) via a sampler (SR) coupled via an A/D converter (ADC), a feed forward equalizer (FFE) and a summator (SUM) to a decision stage (DEC), providing a decision signal fed via an adaptive decision feedback equalizer (DFE) to the summator and to one input of 2 phase detectors (PD1,PD2), receiving the outputs of the A/D converter and the summator at their second inputs respectively. The phase detectors are selectively coupled via a loop filter (LF) to a digitally-controlled oscillator (DCO) connected to the clock input of the sampler. An Independent claim for a clock signal regeneration circuit for a receiver is also included.