A logarithmic low dark current CMOS pixel

摘要

High dynamic range pixels are required in a number of automotive and scientific applications. CMOS pixels provide different approaches to achieve this. However, these suffer from poor performance under low light conditions due to inherently high leakage current that is present in CMOS processes, also known as dark current. The typical approach to reduce this dark current involves process modifications. Nevertheless, energy considerations suggest that the leakage current will be close to zero at a close to zero voltage on the photodiode. Hence, the reduction in dark current can be achieved by forcing a zero voltage across the photodiode. In this paper, a novel logarithmic CMOS pixel design capable of reducing dark current without any process modifications is proposed. This pixel is also able to produce a wide dynamic range response. This circuit utilizes two current mirrors to force the in-pixel photodiode at a close to zero voltage. Additionally, a bias voltage is used to reduce a higher order effect known as Drain Induced Barrier Lowering (DIBL). In fact, the contribution of this effect can be compensated by increasing the body effect. In this paper, we studied the consequences of a negative bias voltage applied to the body of the current mirror pair to compensate for the DIBL effect thereby achieving a very small voltage drop on the photodiode and consequently, a higher sensitivity in low light conditions.