Model-Based CMP Aware RC Extraction of Interconnects in 16nm Designs

摘要

Traditional RC extraction flows mostly consider interconnect thickness variations caused by etch and CMP processes in a way of rule-based approach where a form of tables or polynomials is used. While such rule-based approaches are easily incorporated into design flows, they are not inevitably accurate since table-look-ups in rules are inherently taking simple (mostly one dimensional) typed patterns. Moreover, rules fail to account for the length scale and cumulative effects in both etch and CMP, thereby making them less accurate compared to physics-based models. In this paper, we introduce a model-based CMP aware RC extraction flow that uses the results of thickness simulations from Cadence CMP modeling tools. We apply the proposed model-based CMP aware RC extraction flow to several blocks in a 16 nm design, and compare the results of the proposed model-based flow with those of a traditional rule-based RC extraction flow This paper also notes that running the model-based flow in conjunction with the traditional rule-based flow should cover the full range of RC variation along critical nets, and ensure faster timing closure.