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Estimation of Crosstalk Noise for RLC Interconnects in Deep Submicron VLSI Circuit

机译:深度亚微米VLSI电路RLC互连串扰噪声的估算

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The modeling of interconnections is very much important, as the performance of VLSI circuit is limited by interconnect related failure modes, such as coupled noise and delay. Inductance along with capacitance causes noise in the signals, which may adversely affect the performance of the circuit and signal integrity. An analytical expression for crosstalk noise voltage is derived in this study using L model for RLC global interconnects in deep submicron VLSI circuit. Then the noise voltage is estimated by simulation using HSPICE. The result shows that the L model is good enough to compute crosstalk noise for RLC interconnects.
机译:互连的建模非常重要,因为VLSI电路的性能受互连相关的故障模式的限制,例如耦合噪声和延迟。电感以及电容导致信号中的噪声,这可能会对电路和信号完整性产生不利影响。使用LLC全局互连在深亚微米VLSI电路中的L模型来源于串扰噪声电压的分析表达。然后通过使用Hpice仿真估计噪声电压。结果表明,L型号足以计算RLC互连的串扰噪声。

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