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Estimation of crosstalk noise for RLC interconnects in deep submicron VLSI circuit

机译:深亚微米VLSI电路中RLC互连的串扰噪声估计

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The modeling of interconnections is very much important, as the performance of VLSI circuit is limited by interconnect related failure modes, such as coupled noise and delay. Inductance along with capacitance causes noise in the signals, which may adversely affect the performance of the circuit and signal integrity. An analytical expression for crosstalk noise voltage is derived in this study using L model for RLC global interconnects in deep submicron VLSI circuit. Then the noise voltage is estimated by simulation using HSPICE. The result shows that the L model is good enough to compute crosstalk noise for RLC interconnects.
机译:互连的建模非常重要,因为VLSI电路的性能受到互连相关故障模式(例如耦合噪声和延迟)的限制。电感和电容会在信号中引起噪声,这可能会对电路性能和信号完整性产生不利影响。在本研究中,针对深亚微米VLSI电路中的RLC全局互连使用L模型,得出了串扰噪声电压的解析表达式。然后,通过使用HSPICE进行仿真来估算噪声电压。结果表明,L模型足以计算RLC互连的串扰噪声。

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