Correlation between Defects and Electrical Characteristics/Reliability Analyzed by Integrated Evaluation Platform for SiC

摘要

The Integrated Evaluation Platform for SiC wafers and epitaxial films is established. It provides information about the correlation between step-bunching defects and SiO_2/SiC electrical characteristics/reliability. The Observation-Recognition System discovers that the step bunching on the epitaxial wafer partly spreads along the scratches. The Q_(bd) measured in the Electrical-Characteristics Analyses has three types of distribution denoted as D1 (ideal SiO_2/SiC without defects), D2 (average Q_(bd) value half of D1 with step bunching), and D3 (small Q_(bd) value with large defects). The Defect-Structure Analyses elucidate that the oxide thickness fluctuates on the step bunching line. The local electric field concentration at thinner spots causes degradation of SiO_2/SiC reliability.