Conventional scaling of planar CMOS devices has reached a practical electrostatic design limit at roughly 25nm gate lengths, corresponding to the 20nm node. The double-gate transistor has long been known to offer the potential to extend electrostatic scaling and in the last dozen years, workers around the world, in academia and industry, have applied a vertical fin-like embodiment of the double-gate FET, most popularly referred to as the 'FinFET,' to tackle the challenges of process, device, and product design, and accomplish the introduction of double-gate FETs into main-stream manufacturing. A view of these challenges and their solution leads to a projection that this FinFET structure will prove scalable to at least the atomic limit of CMOS scaling.
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