FinFET Evolution Toward Stacked-Nanowire FET for CMOS Technology Scaling

摘要

The performance of an evolutionary FinFET design (iFinFET) is benchmarked against that of the conventional bulk FinFET and stacked-nanowire gate-all-around (GAA) FET, through3-D device simulations, for both n-channel and p-channel transistors. The results show that the iFinFET provides for improved electrostatic integrity relative to the FinFET, but with substantially less gate capacitance penalty relative to the GAA FET. Thus, iFinFET technology offers a technological pathway for continued transistor scaling with performance improvement, for future low-power system-on-chip applications.