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Simulation to Study the Effect of Variation of Oxide Thickness and Substrate Doping on DIBL in MOSFET

机译:仿真研究氧化物厚度和基板掺杂在MOSFET中掺杂掺杂的影响

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摘要

In this work, the Drain Induced Barrier Lowering is studied as the function of oxide thickness and substrate doping. The effects are verified simulating with TCAD Sentaurus toolkit. High-K dielectric material is used in place of SiO_2. Also investigation of the effect of change in substrate doping on Drain Induced Barrier Lowering is studied.
机译:在这项工作中,研究了漏极感应的屏障降低作为氧化物厚度和衬底掺杂的函数。使用TCAD Sentaurus Toolkit进行了验证的效果。使用高k介电材料代替SiO_2。还研究了对衬底掺杂变化对漏极引起的屏障降低的影响的研究。

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