Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications

摘要

The impact of high permittivity gate dielectrics with different equivalent oxide thickness (EOT) for conventional, low and high tilt angle halo implants on the performance of 100 nm n-MOSFETs device is studied using device simulator Synopsys ISE-TCAD. In this paper, we systematically increase the value of gate dielectric (3.9-50) and investigate its effects on conventional, low angle of tilt (10°) and high angle of tilt (50°) halo implants for different device parameters of 100 nm n-MOSFETs using two different EOT viz. 1.5 nm and 2.0 nm. The impact of gate dielectric permittivity along with the different angles of halo implants on short channel performance contributing to the DIBL, the subthreshold swing, I_(ON)/I_(OFF) ratio, and the threshold voltage V_T are studied for two different EOT thicknesses. The device has been investigated for digital performance parameters like the variation of substrate-body voltage on DIBL, I_(OFF), I_(ON) and the threshold voltage V_T for sub 100 nm technology generation. It has also been investigated for analog performance like trans-conductance generation factor (gm/I_D) and overall gain (gmR_0).