A Novel Method for Delay Analysis of CMOS Inverter with On-Chip RLC Interconnect Load

摘要

In this paper, the behaviour of CMOS inverter driving RLC interconnect load is analyzed. The analysis is based on the modelling of RLC load, developed for submicron devices. Sakurai's alpha-power law is used here for representing the transistor current. Accurate and analytical expressions for the output voltage waveform are derived by solving the system of differential equations which describe the behaviour of the circuit. The 50% delay for on-chip interconnect is then calculated from the transient response. The output response derived from this model is compared with the SPICE simulation results and the results obtained by using the proposed model are in good agreement with SPICE model. The maximum error has been found to be 9.4%.