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Optimum Repeater Insertion Based on a CMOS Delay Model for On-Chip RLC Interconnect

机译：基于CmOs延迟模型的片上RLC互连优化中继器插入

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1. A novel interconnect-optimal repeater insertion model with target delay constraint in 65 nm CMOS [J] . Zhu Zhang-Ming, Qian Li-Bo, Yang Yin-Tang 中国物理：英文版 . 2009,第003期

机译：65 nm CMOS中具有目标延迟约束的新型互连最优中继器插入模型
2. An Explicit Crosstalk Aware Delay Modelling For On-Chip RLC Interconnect for Ramp Input with Skin Effect [J] . Shilpi Lavania, Vikas Maheshwari International Journal of Engineering Research and Applications . 2011,第4期

机译：具有趋肤效应的斜坡输入的片上RLC互连的显式串扰感知延迟建模
3. Closed-Form Delay and Crosstalk Models for $RLC$ On-Chip Interconnects Using a Matrix Rational Approximation [J] . Roy S., Dounavis A. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2009,第10期

机译：使用矩阵有理逼近的$ RLC $片内互连的闭式延迟和串扰模型
4. Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect [C] . Ismail, Y.I., Friedman, . 1998

机译：片上RLC互连基于CMOS延迟模型的最佳中继器插入
5. A theory on repeater-insertion methodologies for SoC interconnects. [D] . Awwad, Falah Rashad. 2006

机译：SoC互连的中继器插入方法论。
6. Development of a Non-Invasive On-Chip Interconnect Health Sensing Method Based on Bit Error Rates [O] . Insun Shin, Kyoungmin Koo, Daeil Kwon 2018

机译：基于误码率的非侵入式片上互连健康感测方法的开发
7. Optimum Repeater Insertion Based on a CMOS Delay Model for On-Chip RLC Interconnect [O] . Yehea I. Ismail, Eby G. Friedman 1998

机译：基于CmOs延迟模型的片上RLC互连优化中继器插入

Optimum Repeater Insertion Based on a CMOS Delay Model for On-Chip RLC Interconnect

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