Embedded Chip-Stack Package

摘要

Continued efforts have been made to reduce the size of electronic devices while simultaneously increasing their functionality, especially in the growing industries including those of wearable computers and medical/healthcare devices. To meet the needs in these areas, we have developed a die embedded package, called WABE (Wafer and Board Level Embedded) Package, which is thin and embedded with one IC chip, by combining a multilayer FPC technology and a thin WLP technology. This package is fabricated by a single step co-laminating process using conductive-paste-filled vias for establishing z-axis interlayer electrical connections. In addition, we have developed a chip-stack embedded package that has two IC chips embedded vertically in a circuit board and put it into use for the first time in the world to meet the demand for package size reduction. This new chip-stack embedded package can be fabricated by almost the same process as a single IC embedded package. We evaluated the reliability of the package (4.35 by 3.00 with 0.40 mm thickness) with seven wiring layers and two EEPROMs embedded in a stacked configuration. We conducted MSL 3 (Moisture Sensitivity Level 3) testing as pre-conditioning. After MSL3 testing, they were put through a temperature cycle test, a temperature humidity bias test and a high temperature storage test. All the modules underwent tests on diode characteristics and functionality and passed all of them. We believe this chip-stack embedding technology is promising to downsize the footprint especially for a package with high functionality and a complex structure.