III-V-On-Insulator MOSFETs on Si Substrates Fabricated by Direct Bonding Technique

摘要

It has been well recognized that new device engineering is indispensable in overcoming difficulties of advanced CMOS and realizing high performance LSIs under 10 nm regime. Fig. 1 shows the future evolution scenario of CMOS device/process technologies presented in the International Technology Roadmap for Semiconductors (ITRS) 2009 edition [1]. In addition to the improvements of gate stacks using metal gate/high k gate dielectrics and the channel electrostatics control using fully-depleted SOI and multi-gate MOSFETs, new channel materials with enhanced carrier transport properties are strongly expected for further increasing current drive and resulting LSI performance. Here, the channel materials with high mobility and, more essentially, low effective mass, are preferable under quasi-ballistic transport expected in ultra-short channel regime [2]. From this viewpoint, strong attentions have recently been paid to III-V semiconductors, SiGe and Ge channels. Because of extremely high electron mobility and low electron effective mass of III-V semiconductors such as GaAs, InP, InGaAs and InAs and extremely high hole mobility and low hole effective mass of Ge, III-V materials and Ge are suitable for n-MOSFET and p-MOSFET applications, respectively. According to Fig. 1, the timeline for introducing SiGe and III-V channels has set at 2016 and 2019, respectively.