Implementation of AES-128 Algorithm Based on FPGA

摘要

This paper presents the implementation of nonpipelined codec of AES-128 algorithm designing. Under full consideration of this algorithm, we reconstructed the iterative steps to reduce the complexity of the calculation process by sharing Sboxes, which greatly improved the utilization of resources. We have proposed the inverse key expansion algorithm, which dynamically generates the decryption round keys in order to saving resources. This method is suitable for the application of the low-cost encryption and decryption chip that the data throughput is not critical.